library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Entity declaration for the AND gate
entity AND_Gate is
    Port (
        A : in STD_LOGIC;  -- First input
        B : in STD_LOGIC;  -- Second input
        Y : out STD_LOGIC   -- Output
    );
end AND_Gate;
 
-- Architecture definition
architecture Behavioral of AND_Gate is
begin
    -- Process to implement the AND logic
    Y <= A and B;  -- Output Y is the logical AND of inputs A and B
end Behavioral;

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